1. Field of the Invention
The present invention relates to a cache memory control system, and more specifically to an error correction code generation method for use in writing data to cache memory and a cache memory control device for controlling the generation of error correction codes.
2. Description of the Related Art
A system for storing some data from a main memory in a cache memory that is close to the central processing unit (CPU) of a computer to improve the processing speed of the CPU has conventionally been used. The data stored in the cache memory is protected by adding an error correction code (ECC).
However, with the recent technology of downsized semiconductor, the storage elements configuring RAM used as cache memory have also been downsized, and stored data are easily inverted. In the circuit inside the RAM, the margin for controlling internal operation timing is often reduced to improve the operation frequency, thereby restricting the voltages and the temperatures at which operations can be performed and resulting in a lower reliability in holding data against fluctuations of voltage and temperature.
With the situation above, faults occur in various modes in cache memory. In the first mode, a software error occurs in which an inverted value of a RAM cell is generated due to the conflict of, for example, an alpha ray. In the second mode, the value of a RAM cell is not correctly updated when data is written. In these first and second modes, the values in the RAM are destroyed.
In the third mode, the value of a RAM cell is inverted due to the charging of a read line when the value of the RAM cell is read. In the fourth mode, the correct value of a RAM cell is not read due to write recovery troubles.
The write recovery troubles may be, for example, an error in SRAM, which is a phenomenon in which the margin for carrying out the reading of data in the subsequent cycle is reduced because written data, immediately before it is read, stays on the bit line when the data is read immediately after the data is written to the SRAM. When this phenomenon occurs, the delay time is extended when it is not severe and a read error occurs when it is severe.
The influence of the fault of the RAM on the generation of an ECC is described below by referring to FIG. 1. FIG. 1 is an explanatory view of the conventional technology in the error correction code generation system used when data is written to cache memory. In this example, it is assumed that one line in cache memory has 8-bytes. The conventional system of generating an error correction code is described below by assuming that data is written to the first half of a line, i.e., 4-bytes.
In the conventional system shown in FIG. 1, data in the cache line for storage in the cache memory is checked by a store instruction issued from an instruction unit in the CPU. After it is confirmed that no errors are contained in the cache line for storage, the store data actually received from, for example, an arithmetic unit, is written to the cache memory. FIG. 1 is an explanatory view of the generation of an error correction code when store data is written to the cache memory as the second stage after confirming that no errors are contained in the cache lines for storage.
First, in cycle 0, the store data output from the arithmetic unit is stored in the store buffer (STB) and supplied as write data to the cache memory in cycle 1. In cycle 1, the data in the cache line for storage in the cache memory, that is, the cache line in which it is confirmed at the first stage that there are no errors, is simultaneously output and merged with the store data stored in the store buffer in cycle 2. In cycle 3, an error correction code is generated for the data as a result of the merger. In cycle 4, the ECC is registered in ECC storage RAM for storing an ECC. That is, for higher speed cache access, an ECC is generated after updating cache data.
In the conventional technology described by referring to FIG. 1, even if no errors are detected in the cache line for storage in the cache memory at the first stage, a RAM error can occur in the process from the first stage to the second stage. If such an error occurs, then, for example, a 1-bit error can occur in the four bytes of the second half, which are not supposed to be stored data in the cache line that will be read from the cache memory at the second stage, and the cache line data referred to data in a cache line herein, is merged with the store data. As a result, a problem can arise in which a correct error correction code cannot be generated for the stored data. In this case, the stored data is not correct. Therefore, even if the error is detected by, for example, a parity check, the error cannot be corrected, and the error is processed as an irrevocable error. When RAM read troubles occur in reading a cache line for merging data, it is necessary to process an irrevocable error by suppressing the use of the data, which is a problem.
Patent document 1, as the conventional technology for correcting an error for cache memory, discloses the technology for reducing the overhead for detecting and correcting an error by providing a plurality of check bits for data bytes to check and correct an error in a pipeline system in the cache memory.
Patent document 2, as the conventional technology for correcting a software error, discloses the technology for checking the parity of data in a cache line, using the data as is without correcting an error if no parity error has been detected, and correcting an error if an error has been detected.
However, the conventional technology cannot solve the problem that a correct error correction code cannot be generated for stored data if an error has occurred after confirming that there is no error in the data stored in the cache memory until store data is actually written to the cache memory.    [Patent Document 1] Japanese Published Patent Application No. H3-108041 “Error Checking in Pipeline System/Corrected Cache Memory and Cache Memory Array”    [Patent Document 2] Japanese Published Patent Application No. 2004-514184 “Method and Apparatus for Correcting Software Error in Digital Data”